3-bit b. Use J-K flip-flop. –Satisfies the above I/O definitions. (10%) 6. Design a counter to produce the following binary sequence. 9. Plot the next-state maps from the table. 2. The clear input is asynchronous. Show transcribed image text Design a counter to produce the following sequence. Connect the IC-type 555 timer unit shown in Fig. 4. 00 01 10 11 Design Specifications • Design a finite state machine controller that meets the following criteria. False – if clock is low, inputs do not affect outputs (b) Flip-flop delays from the change in the clock edge to the change in the output Design a two-bit up/down counter using the microprogrammed flip-flops to negative edge triggered flip-flops to match with the X register. I'm not sure what is meant by parallel load GATE Previous Questions on Latches & Flip – Flops with Solutions (1987 – Till Date) implement in X-Y flip flop using a J-K flip flop ring counter is made by Logic Diagram of Sequence Detector 36 Sequential Circuits with different JK Synthesis 00 11 10 01 0 0 0 1 1 Synthesis Using T Flip Flops Design a counter that Ripple counters: series of complementing flip-flops with the output of each flip-flop connected to the C input of the next one. If JK inputs are 01, JK flip-flop is in reset mode, while the inputs are 10, JK flip-flop is in set mode. Implement the counter using D flip flops and whatever gates you like. D2+ = q1q0'I. See solution for Problem 5-7 Page: 3. When a sequence of 0’s and 1’s is applied to the X input, the output of the network is Z =1 If the total number of 1 inputs received is odd. 11-21 and use it to produce clock pulse that will trigger the flip-flops in the counter circuit. hi im new here. This is a code in which consecutive valuations diﬀer in one variable only. D– This is our input data. 5-MΩ resistor is coded with green, blue, and yellow stripes. In the second method, the output from each flip-flop is used as an input to all the higher-order bits. Now starting from the excitation, you can repeat the derivation of the excitation equations for JK flip flops. Introduction to Sequential Logic Circuits Tutorial. Draw the corresponding sequential circuit. Assign states: S0 00, S1 01, S2 10 and S3 11. SI SO so o 1 o 1 Mode up down modulo 3 modulo 3 YlYo 00 01 10 205 00 01 10 00 11 01 11 00 10 01 11 01 10 00 00 10 01 10 00 00 BUILD 1/2N-FREQUENCY DIVIDERS WITH J-K FLIP-FLOP I strongly recommend you to look back at Figure 1. (0 is an even number). You do not have to draw the circuit diagram. Explain the working of 4-bit synchronous counter with the help of timing diagram. CSC9R6 Computer Design. D Flip-Flop Example §Design a sequential circuit When the sequential circuit is in present state 00 and the in Sequential Circuit with JK Flip-Flops (1 (b) With logic diagram and truth table explain the working JK Flipflop. – Consider using a counter when many FSM states with few branches. Using the given conditions draw the design. When E = 1 and x = 0, the circuit Example Sequential Circuits (cont’d) • Counters ∗ Easy to build using JK flip-flops » Use the JK = 11 to toggle ∗ Binary counters » Simple design – B bits can count from 0 to 2B−1 » Ripple counter – Increased delay as in ripple-carry adders – Delay proportional to the number of bits » Synchronous counters Four Bit Asynchronous Down Counter. using just three flip flops and draw a state transition diagram, state table and a schematic your counter should produce the sequence 0000, 0001, 0011, 0010, 0110 sequence of zero (0000) through 9 (1001) is a BCD decade counter because its 10-state sequence produces the BCD code. Bring your textbook to the lab! Devices used: sn74LS00 Quad 2-input NAND sn74LS76 Dual JK Master-slave flip flop 2732A EPROM MAX3000 EPM3032ALC44-10 CPLD Digital-to-Analog converter (DAC) Op Amp Experiment: Latches and Flip-flops 1. Using T flip-flops, design a circuit for the following state diagram. . Use T flip-flops. Show transcribed image text Design a counter to produce the following sequence. 3 Background state,10 Mathematically, NAND 11 0 which the counter will sequence. 10. In the previous section, we saw a circuit using one J-K flip-flop that counted backward in a two-bit binary sequence, from 11 to 10 to 01 to 00. Design a circuit that provides In other words, the LSB will oscillate at the highest frequency, followed by the next bit at one-half the LSB’s frequency, and the next bit at one-half the frequency of the bit before it, etc. (4) ii. 1. Using JK flip-flops, design a circuit for the following state diagram. For simplicity, we limit the design to one input and 2 JK flip flops. So we add columns to the state table showing the input required to each JK flip-flop to cause the correct state transition. If E = 0, the circuit remains in the same state, regardless of the input X. The logic Design. Asynchronous counters are known as (a) ripple counters (b) multiple clock counters (c) decade counters (d) modulus counters 36. Assuming the circuit below begins in state 0,0,0, write the sequence of states that occurs in the boxes given below the flip-flops. When E = 1 and X = 1, the circuit goes through the state transitions from 00 to 01 to 10 to 11, back to 00, and then repeats. Toggle (T) flip-flops are used to design the counter circuit. ). Design of synchronous sequential circuits with an example. Stroud ELEC 4200 7 (20 points) Design a 4-bit counter which counts in the sequence 0000, 0001, 0011, 0111, 1111, 1110, 1100, 1000, 0000 using clocked D flip-flops. A decade counter requires 4 flip-flops. A 4 bit ripple counter and a 4 bit synchronous counter are made using flip-flops having a propagation delay of 10 ns each. (a) Implement the switching function whose octal designation is 274 using NOR gates only. But we can use the JK flip-flop also with J and K connected The 3-bit up counter can be implemented using S-R flip-flops and D flip-flops. Counters are of two types. Using SR flip-flops, design a synchronous counter which counts in the sequence 000, 111, 101, 110, 001, 010, 000, (16) Design a mod – 5 synchronous counter using JK flip – flops with separate logic circuitry for each J and K input. 00, 10, 01, 11,00, Design a counter to produce the following binary sequence. Design a counter using either D or JK flip-flops that will count The 5-bit sequence 10001 tells a separated by the pipelining flip-flops DFFPS. Decade 4-bit Synchronous Counter. Asynchronous or Ripple Counters. (a) Module- M13 The module M13 is a parallel synchronous 3-bit up counter using JK flip-flops. (b) Design a counter with the following repeated binary sequence: 0. Use R A = 0. Examples:- For N=3, from the above equation, n=2 i. i have this problem in my science class we are going to put this design a 4 bit even counter design using jk flip-flop (0,2,4,6,8,0 so on. Show that when binary states 010 and 101 are considered as don’t care conditions, the counter may not operate properly. The only time we use it is to pull it low in order to force Q to a logic zero output. 16. – Learn how to reset a 4-bit binary counter to recycle after 9. e. Problem 2 . Also obtain its characteristic equation. Present Present Next State Output AB S X=0 X=1 Z 00 S0 S1 S2 0 01 S1 S1 S2 1 10 S2 S2 S3 1 11 S3 S3 S0 0 00 01 11 10 0 1 AB X Db Db = XAB’ + X’A’ + X’B 11 00 01 gray code: 00 01 11 10 binary: 00 01 10 11 one-hot: 0001 0010 0100 1000 (reminds one of an decoder's outputs) (note: if we have three states or ten, we just use 10 bits and move from left to right making one variable equal to 1 at a time) notes: n = number of states 1. Use JK flip-flops 07 Flip-Flop Applications produce a specified output pattern sequence Types of counters synchronous mod-6 counter using clocked JK flip-flops. And the output terminal should be the Q terminal of the last J-K flip-flop. A counter goes through a predetermined sequence of states. Use JK flip-flops. 5. 11. We propose to implement this type of MOD-6 J-K flip-flop direct counter because, together with the T type flip- flops, the J-K flip-flops are usually used in creating the counters (being flip-flops order 2). We need two flip-flops, one for each bit. 3. Synchronous Sequential Machines or flip-flops. When E = 1 and x = 1, the circuit goes through the state transitions from 00 to 01 to 10 to 11 back to 00, and repeats. i. J-K Flipflop Edge-Triggered Flipflops 00 01 11 10 0 0 X 1 1 0 X 1 0 1 Q ( t ) S Contemporary Logic Design " This guarantees following stage will latch current When the input is high, the counter should sequence through three states: 10, 01, 11 and repeat. There are many different ways to construct flip-flops, but they all exhibit the following two characteristics: • a ff will change state only on the positive or negative edge of the clock signal. b) design the one-flip-flop-per-state circuit to implement the state machine. If E =0, the circuit remains in the same state regardless of the value of x. microprogrammed control which uses a memory device to produce a sequence of control words to a datapath. One way to make the counter recycle after the count of 9 Design a sequential circuit with two JK flip-flops A and B and two inputs X and E. Use RA = 0. The toggle(T) flip-flops are being used. 01 00 11 1 0 10 00 10 • Design the circuit using JK flip-flops Design a counter that counts from 0 to 7 and Depending on the 2-bit select input (M), the shift register is either to: 00 – No change, 01 – Parallel Load, 10 – Rotate left, 11 – Shift right (with SI). [6M] b) Design Mod-5 counter to count the sequence 0,1, 3, 7,6. 20 Points . ceiling (log2(n)) = number of flip flops needed (for gray code and binary equations for D and JK flip-flops. Step 3: Let the three flip-flops be A,B,C. Construct a state table showing the present state and the next state including any don’t cares marked with x’s. 1. Consider the state table given in Fig. Form a state table which gives the next flip-flop states for each combination of present flip-flop states. Design a counter that counts in the sequence: 000, 010, 001, 100, 011, 110, 000, Use clocked T ip-ops. For example 00, 01, 11, 10, 00 … is a two-bit Gray code. Using SR flip-flops, design a synchronous counter which counts in the sequence I would probably use two bits to encode the three switches, and the general approach would be to have a string of pairs (one for each bit) of D or JK flip-flops to accept the sequence of input digits, essentially a shift register for pairs of bits. Q(T) Q(T + 1) J K 0 0 0 d 0 1 1 d 1 0 d 1 1 1 d 0 Steps 7 and 8 are skipped in this lecture. Design a counter to produce the following sequence. 0,9,1,8,2,7,3,6,4,5,0,. Consider the sequential network Lab 1: Study of Gates & Flip-flops Aim To familiarize with circuit implementations using ICs and test the behavior of different logic gates and Flip-flops. Plot a T input map for each flip-flop. We use JK flip-flop circuits because they are of order 2 and no state of indetermination. A standard binary counter can be converted to a decade (decimal 10) counter with the aid of some additional logic to implement the desired state sequence. −A decade counter has 10 states which produces the BCD code. Use a minimum number of additional logic gates. Problem 3 . 6. When reset, the output should be 000. Your design should include circuitry to ensure that if we end up in an unused state, the next clock pulse will reset the counter to T 2 T 1 T 0 =000. 00 0 0 0 11 11 1 10 equations for D and JK flip-flops. We need N J-K flip-flops to build 1/2n-frequency dividers. The pinout is shown in Figure 4. Or (b) Design a switching circuit that converts a 4 bit binary code into a 4 bit Gray code using ROM array. 1 to count DOWN instead, is simply a matter of modifying the connections between the flip-flops. This video is the first of three videos showing how to design a counter with an arbitrary sequence using JK flip flops. – Learn how to build an asynchronous 4-bit binary counter using a toggle flip-flop. • its data inputs must not change after time t setup and before t hold . Design a two bit counter (a sequential circuit) that counts from 00 to 10 only. The flip-flops are cleared to ‘0’ at the R input. 00, 10, 01, 11, 00, . The feedback logic is to be designed to obtain the count sequence shown in the same figure. 047 F. Use J-K flip-flops. 13. (11%) 7. Page 8 of 10 Design a sequential circuit with two JK flip-flops A and B and two inputs E and x. B is a J-K flip-flop, so we determine the function for B+ by substituting the logic functions at the J and K inputs into the J-K excitation function. For the next state part of the table, each entry defines the value of the sequential circuit in the next clock cycle after the rising edge of the Clk . Chapter 7 EGR 270 – Fundamentals of Computer Engineering Topic 01: Review, pg. Write the excitation table and state table. Answer The next-state and transition tables for the counter could be defined as: Q2 Q1 Q0 Next-state 0 0 1 1 Elec 326 3 Sequential Circuit Analysis 10. External clock is applied to the clock input of flip-flop A and Q A output is applied to the clock input of the next flip-flop i. When E =1 and x=1, the circuit goes through the state transitions from 00 to 01 to 10 to 11 back to 00,and repeats. when AB = 00, 01, 10 and 11. in mod-10 counter (final count 1010) 2 nd and 4 th flip flops from left are in high state. 6-9), logic diagram (Fig. Synchronous counters. Design a 3-bit Gray code counter FSM with no inputs and three outputs. Asynchronous or ripple counters. Obtain the Characteristic Equations for the following Flip -flops (i) JK (ii) SR 6M c. 12 Flip-flops have a number of applications, several of which are discussed here. Due 1/25/01 1. Analyze the final circuit to ensure that it is self-correcting. It is the value we wish to set Q to. Design a counter with the following repeated binary sequence: 0, 1, 2, 4, 6. Flip-flops are the basic logic elements used in sequential logic. Once it reaches the count 9 (1001 in binary), the counter goes back to 0000 instead of continuing on to 1010. On each clock edge, the output should advance to the next Gray code. 10 00 From the above excitation map and using a K-Map, we can derive the excitation equations of the flip flop: D1+ = q0I' + q1q0'I. Spring 2006 Slide 52 Karnaugh Maps 00 01 11 10 1 0 BC A. Count-down Counter [ 3 marks ] Design a 2-bit count-down counter. Use T flip‐ flops. The 10-MΩ resistor is coded with brown, black, and blue stripes and the 0. (16) (N/D-10) 6. Using JK flip flops, design an up/down synchronous counter that counts from 3 to 6. Decima l Binary 0 000 1 001 3 011 5 101 7 111 13) Design synchronous counters that go through each of the following sequences: 6 5 1 3 7 and repeat Using JK flip-flops. I'm not sure what is meant by parallel load Design a counter with T flip‐‐flops that goes through the following binary repeated sequence: 0, 1, 3, 7, 6, 4. Otherwise the output is Z = 0. (c) Design a counter with the following repeated binary sequence: 0, 1, 3, 5, 7. Recall our analysis example… We derived the following state diagram. Design a MOD Synchronous counter using SR flipflop. Solution: From the ﬁgure it follows that g2 Connect the IC-type 555 timer unit shown in Fig. Since it would be desirable to have a circuit that could count forward and not just backward, it would be worthwhile to examine a forward count sequence Modulus 10 Counter. 12. Asynchronous counters. Question . Also known as ripple counters, as the input clock pulse “ripples”through the counter –cumulative delay is a drawback. You will learn to derive the combination logic that meets the design specifications. state transitions from 00 to 01 to 11 to 10 back to 00 and repeats. 5 M RB = 20 M and C = 0. (16) 2. In electronics, counters can be implemented quite easily using memory devices such as Flip-flops. For this ASM, a) design the minimum flip-flop circuit to implement the state machine. Start the design with a D FF (MSB), a T FF, and a JK FF (LSB). You may make the 8. Discrete Components – 74LS00 Quad 2-Input NAND gate 74LS02 Quad 2-Input NOR gate 74LS04 Hex 1-Input NOT gate Flip-flop Review. D 1 = C'Q 1 + Q 0 CQ 1 ' + CQ 1 Q 0 ' Equation 1. J-K Flip-flop Binary Counter A Counter is a device, which stores (and sometimes displays) the number of times a particular event has occurred, often in relationship to a CLOCK Signal. The schematic is shown in Figure 2. Fig 2. Compare Moore and Mealy circuits. Here the J and K inputs of all the flip flops are shorted and thus its operation is equivalent to a T flip-flop. Design a counter with the sequence 0, 1, 3, 7, 6, 4, 0. When x=1 the circuit goes through the state transition from 00-01-11-10-00 and repeats. Design a counter made from JK flip-flops to produce a three-bit Gray code. ENABLE – T2 = Q0 . The 10-M resistor is coded with brown, black, and blue stripes and the 0. Counter Design with D Flip-Flops Next state maps and flip-flop inputs AB U 00 01 0 1 11 10 1 1 X X AB U 00 01 0 1 11 10 1 X X 1 A+ = D A = UB + U’A’B’ B+ = D The Design of the Moebius Mod-6 Counter Using Electronic Workbench Software containing two J-K flip-flops) or using t wo the design of direct mod 6 down counter is proposed by using J-K A J-K flip-flop with J = 1 and K = 1 has a 10 kHz clock input. Give design details. Our discussion will focus on behavioral models. But we can use the JK flip-flop also with J and K connected permanently to logic 1. Department of the Space Sciences [5th Semester, Session 2009-13] 27 Types Of The Counters: Counters are generally divided into two following types: 1. Thus, the counter states are 00, 01, 10, 00, 01,…. • Use JK flip-flops and suitable logic gates to design a 4-bit binary Gray code generator. C. Draw and explain the block diagram of Mealy circuit. 6-10). 53 depicts the conversion between three-bit binary and Gray codes. When E =1 and x=1, the circuit goes through the state transitions from 00 to 01 to 10 to 11 back to 00, and repeats. Use D flip‐ flops. Design a circuit that provides Hello I am doing the grade 11 computer engeneering course and I was doing my homework when I got stuck on a question that says "Design a counter using J-K flip flops that will count in the following sequence: 0,2,5,1,3" would some one please help a newbie like my self make this counter. The design for this counter is done using JK flip flops and is a fairly involved A Synchronous Counter Design Using D Flip-Flops and J-K Flip-Flops For this project, I will show how to design a synchronous counter which is capable of storing data and counting either up or down, based on input, using either D flip-flops or J-K flip-flops. Design a counter with the following binary sequence 0, 1, 9, 3 1. Circuits may be built that “count” in a binary sequence, using J-K flip-flops set up in the “toggle” mode. Use JK flip‐flops. If E =0 ,the circuit remains in the same state regardless of the value of x. Design a MOD 6 Synchronous counter using T flipflop. • Counters simplify “controller” design by: – providing a specific number of cycles of action, – sometimes used with a decoder to generate a sequence of timed control signals. Binary ripple counter: T flip-flops or D flip-flops (Fig. 00 11. (12) 3. Registers are constructed using one or more flip-flops which share common signals such as the clock. The missing transitions are from state 01 to 00 on input 0, 10 to 00 on input 0, and 11 to 11 on input 1. We give the next-state and output K-maps in Figure 8. 0,10,01,11,00,… 7. BUILD 1/2N-FREQUENCY DIVIDERS WITH J-K FLIP-FLOP I strongly recommend you to look back at Figure 1. After reaching 100, it should repeat with 000. Design your counter to go to state 000 from all invalid states. (5) (a) Design a counter which produces the following binary sequence: 0, 1, 3, 7, 6, 4 and then repeats. 4 (p. (20 points) Design a sequential circuit that behaves in the following way. Using SR flip-flops, design a synchronous counter which counts in the sequence 000, 111, 101, 110, 001, 010, 000, (16) 4. Using D flip-flops and basic gates, design a counter that counts in the following sequence: (8) 1, 5, 6, 1, 5, 6, 1, 5, … The contents of the flip-flops are the binary equivalent of the count. Explain the rules for state reduction in synchronous A Synchronous Counter Design Using D Flip-Flops and J-K Flip-Flops For this project, I will show how to design a synchronous counter which is capable of storing data and counting either up or down, based on input, using either D flip-flops or J-K flip-flops. The RS latch is the fundamental element in sequential Design a FSM circuit with two JK flip-flops A and B and two inputs E and x. Assignment 3 Group: Name: ID: 1. Use three clocked T flip-flops and logic gates only. 2, find the original sequential network using JK flip-flops. 5 MΩ, R B = 20 MΩ, and C = 0. 5 Counter Design Using S-R and J-K Flip-Flops 00 01 0 1 11 10 1 1 1 1 BC A 00 01 11 10 0 x x 1 1 1 0 0 1 0 Design a 3 bit counter which counts in the sequence: Implementation using J-K flip-flop. By taking both the output lines and the CK pulse for the next flip-flop in sequence from the Q output as shown in Fig. hardwired control which includes techniques such as “one-hot-state” (also known as "one flipflop per state") and decoded sequence registers. c. Implement a counter to produce a specified sequence of states. The binary number is shifted out from one side and it’s 2’s complement shifted into the other side of the shift register. (b) Design a counter with the following repeated binary sequence: 0, 1, 2, 4, 6. Step 2: Let the type of flip-flops be RS flip-flops. 0 0 o When UP = 1, the counter counts up in the sequence 00, 01, 10, 11, 00, … o When UP = 0, the counter counts down in the sequence 00, 11, 10, 01, 00, … • An active-low asynchronous clear, CLR_BAR o When CLR_BAR = 0, the count is reset to 00 • A falling-edge triggered clock, CLK To complete this experiment do the following: 1. (10 pts) Determine the D ﬂip-ﬂop excitation equations for the system represented with in the state-transition table below. Next state equations use the excitation Changing from 00 to 11 can produce nondeterministic 00 01 11 10 Q(t+1) Elec 326 16 Flip-Flops Elec 326 17 Flip-Flops Alternative Design of the gated D Latch 7. These are present states as shown in the table. • Use the output of the Gray code generator as inputs to a combinational logic circuit to decode the Gray code to produce the normal binary counting sequence. Q 2. Transition table for a J-K Flip-Flop The following diagram shows the steps to create separate Synchronous Up-Counter using T Flip-Flops • For a 4-bit Up-Counter, the input Ti is defined as: – T0 = 1 – T1 = Q0 – T2 = Q0 . Mealy and Moore Model State Diagrams 00 01 10 11 0/0 1/0 using the graphic design editor before coming to the lab. d 11 00 01. (a) Implement a binary serial adder using an SRFF programmable logic array. Present Next Flip-flop Other flip-flops. Similarly, for N=10 and N=16, we will get n=4. Use JK Flip-Flops. Q1 A Gray code is a sequence of codes which differ in one bit position at each step. Design a It is a group of flip-flops with a clock signal applied. 24 Design a 2-bit up, down, modulo-3, counter with the following function table using JK flip- flops. 16MHz ÷64 3 Spring 2013 EECS150 – Lec22-counters Page Controller using Counters A mod-16 Counter We can use JK flip-flops to implement a 4-bit counter: Note that the Jand Kinputs are all set to the fixed value 1, so the flip-flops "toggle". Spring 2006 Slide 80 J – K Flip Flops Issuu is a digital publishing platform that makes it simple to publish magazines, catalogs, newspapers, books, and more online. Digital Electronics – Counters. You may make the Design a sequential circuit with two JK flip-flops A and B and two inputs X and E. Below is an example of a synchronous binary counter, implemented using J-K flip- flops and AND gates. How JK flip-flop is the refinement of RS flip-flop? 07 OR Q. Synchronous Sequential Circuits Use the characteristic equation for JK flip-flops: 00 01 01 0 0 01 10 10 0 0 10 using just three flip flops and draw a state transition diagram, state table and a schematic your counter should produce the sequence 0000, 0001, 0011, 0010, 0110 GATE Previous Questions on Latches & Flip – Flops with Solutions (1987 – Till Date) It is desirable to convert a J-K flip flop into X-Y flip flop by adding some external gates, if necessary. These equations describe the inputs to the flip-flops in terms of the current circuit inputs and current circuit state. 16MHz ÷64 3 Spring 2013 EECS150 – Lec22-counters Page Controller using Counters following sequence: SIS2=00/01/11 The lock then remains set for all successive combinations of Sl and S2 until the following release sequence is given: SIS2=11/10/00 Design a suitable asynchronous logic circuit for this application, using NAND gates only, or NAND gates and RS flip-flops. A two-bit asynchronous counter is shown below in fig. Draw the state diagram and state transition table b. that decode the various states of the counter to apply the correct logic levels to the J-K Then we can use the following model of latch behavior: 00 01 11 10 Q(t+1) Elec 326 16 Flip-Flops Elec 326 17 Flip-Flops Alternative Design of the gated D Latch Asynchronous counters In the previous section, we saw a circuit using one J-K flip-flop that counted backward in a two-bit binary sequence, from 11 to 10 to 01 to 00. Design a circuit that can convert a binary code into a Gray according the ﬁgure. BUILD DIVIDERS WITH D FLIP-FLOP LOOPS c 10. separated by the pipelining flip-flops DFFPS. In general, the flip-flops we will be using match the diagram below. a) Explain the SR- Flip- Flop and JK Flip- Flop with NAND diagrams. Other flip-flops. Step 2: Develop next state equations. Develop a next-state table for the specific counter sequence. Analyze what happens to the output at time +1 for all the different combinations of the and inputs. Example: 2-bit synchronous binary counter (using T flip-flops, or JK flip-flops with identical J,K inputs). Present Present Next State Output AB S X=0 X=1 Z 00 S0 S1 S2 0 01 S1 S1 S2 1 10 S2 S2 S3 1 11 S3 S3 S0 0 00 01 11 10 0 1 AB X Db Db = XAB’ + X’A’ + X’B 11 00 01 a J-K flip-flop S 1 0 S 2 1 00,01 01,11 10,11 00,10 Output variables written under state Variable names If S 1 is present state, then If JK=00 and 01 machine remains state S 1 and output is 0 If JK=10 and 11 transition to state S 2 and the output changes to 1 If S 2 is present state, then If JK=00 and 10 machine remains state S 2 and output is 1 These counters use JK flip-flops connected in the toggle mode, with J = K = 1. 60. Q 1. This is a JK flip-flop, so shouldn't it say: The JK flip-flop augments the behavior of the SR flip-flop (J=Set, K=Reset) by interpreting the J = K = 1 condition as a "flip" or toggle command. 4) A PN flip-flop has four operations: clear to 0, no change, complement, and set to 1, when inputs P and N are 00, 01, 10, and 11, respectively. 14. [6M] A B goes through the state transitions from 00 to 1 to 10 to 01 back to 00 and repeats. Let be the state of output at time . 11 oo 01 o 10 nn . Modeling Sequential Logic with Verilog This section introduces some basic models of sequential logic using Verilog. Logic Diagram of Sequence Detector 36 Sequential Circuits with different JK Synthesis 00 11 10 01 0 0 0 1 1 Synthesis Using T Flip Flops Design a counter that Chapter 7 – Latches and Flip-Flops Page 4 of 18 From the above analysis, we obtain the truth table in Figure 4(b) for the NAND implementation of the SR latch. And Draw and discuss the circuit of a dual scope A/D convertor. use JK FFs in Spring 2011 ECE 301 – Digital Electronics 3 Counters 00 10 11 01 Design the following counter using D Flip-Flops . 3 shows a T flip-flop constructed from a JK flip-flop. 2 flip flops are required for MOD-3 counter. Mealy Model Some Inputs Some Combinational Circuit Flip-flops . *(d)Design a counter with the following repeated binary sequence: 0, 1,3, 7, 6, 4. Design a BCD counter using T flip flops, where flip flop inputs are TQ 1, TQ 2, TQ 4 and TQ 8. Equipments – Digital IC Trainer Kit b. Use JK flip-flops to design a counter with the following repeated binary sequence 0 1 2 4 5 6? 8 The waveforms in Figure 10–93 are applied to the count enable, clear, and clock inputs as indicated. Chapter 7 – Latches and Flip-Flops Page 4 of 18 From the above analysis, we obtain the truth table in Figure 4(b) for the NAND implementation of the SR latch. The problem stipulates JK flip-flops, so we use them. List the 10 states produced with five flip-flops and the Boolean terms of each of the 10 AND gate outputs. When E=1 and X=1, the circuit goes "up" through the state transitions from 00 to 01 to 10 to 11 and back to 00, then repeating. using Gray code. The pulses to be counted are applied to the clock input of the first JK flip-flop. However, when X=1, the state sequence is 11, 10, 01, 00, then back to 11 and the sequence repeats. FF-B. 00 01 11 10 Maximum effort was made to minimize the design area on chip. If E = 0, the circuit remains in the same state regardless of the value of x. If E=0, the circuit remains in the same state regardless of the value of X. Q2 Mention the various A/D convertors. Design a MOD 6 Synchronous counter using JK flipflop. You should show the state table, state diagram, the k-map for circuit design and logic diagram of the resultant design using D flip-flop or J-K flip flop. Flip flops v. The respective outputs are 1, 0 The two basic strategies for the design of a controller are: 1. This is common with JK flip-flops. The logic diagram of a 2-bit ripple up counter is shown in figure. Design a MOD – 10 synchronous counter using JK flip-flops. 7- A digital system has a clock generator that produces pulses at a frequency of 80 MHz. The count has a repeated sequence of six states, with flip flops B and C repeating the binary count 00, 01, 10 while flip flop A alternates between 0 and 1 every three counts. a synchronous BCD counter. A ripple counter using negative edge triggered D flip-flops is shown below. . Gate Questions on Flip-flop, Counters and Shift-Registers. As the clock signal runs, the circuit will cycle its outputs through the values 0000, 0001, 0010, . As with other mod counters, it receives an input clock pulse, one by one, and counts up from 0 to 9 repeatedly. To obtain a truncated sequence, it is necessary to force the counter to recycle before going through all of its possible states. Four J K flip flop was stacked on top of Design a sequential circuit with two JK flip-flops, A and B, and two inputs, E and x. 7) Design a sequential circuit with two D flip flops A and B and one input x. Use T-Flip Flops for your implementation. g. The toggle (T) flip-flop are being used. The logic Use the following assignment s: a=00, b=01, c=10, d=11 Problem 2 (20) Use JK Flip Flops to design a sequential circuit for the following assigned state table: Logic Diagram of Sequence Detector 36 Sequential Circuits with different JK Synthesis 00 11 10 01 0 0 0 1 1 Synthesis Using T Flip Flops Design a counter that ab 00 01 11 10 00 x x x x 01 1 1 1 0 11 1 1 1 1 10 x x x x kb = a’ + b + s1 + s2‘ Question 2: Sequential Circuit Analysis The sequential circuit in Figure 2 is a sequence detector that asserts its output Z when a 4-bit serial input sequence is detected. Use T flip-flops to design a decade counter which counts in the Gray-code sequence. Easily share your publications and get them in front of Issuu’s Example: Design a 5-bit synchronous up/down counter using the inspection method and JK flip-flops. Or (b) Using D flip–flops, design a synchronous counter which 3 bit counter Count Sequence: 6 – 3 – 1 – 4 – 6 – 3 – . [6M] A B Design a 3-bit counter using rising edge triggered j-k master-slave flip-flops with the counting sequence 1,4,2,7,1,4,2,7, Use the outputs of the flip-flops as the output of the counter (Moore design). Step 6 – Decide on the type of flip-flops to be used. 00 0/0 1/0 01 11 0/1 1/1 1/0 0/0. 2) Construct a JK flip-flop using a D Flip-flop, a 2-to-1 line multiplexer and an inverter. (16) (A/M-11) 5. 370) In summary, the following procedure can be used to design a counter using T flip-flops: 1. where n is the number of flip flops required. This is a sequential circuit with two flip-flops and one input X. Begin the design by sending all illegal states to state 011 (3). 6. All of them should be cascaded. (11%) 8. Lab 1: Study of Gates & Flip-flops 74LS73 JK-Flip flop 74LS74 D Flip flop 1. Figure 6. When the input is low the counter should sequence through the same states in the opposite order 11, 01, 10 and repeat. latches •Flip flops are edge triggered •Latches are level sensitive Many variants •S-R, J-K, D, T latch/flip-flop •D-type most useful in processor design Beware of race conditions •Need edge triggered device in any feed-back path • Create state table • Choose flip -flops (D, T, SR, JK) • Create circuit excitation table – use flip -flop excitation tables • Construct K-maps for: – flip -flop inputs – primary outputs • Obtain minimized SOP equations • Draw logic diagram • Simulate to verify design & debug as needed C. Use the following assignment s: a=00, b=01, c=10, d=11 Problem 2 (20) Use JK Flip Flops to design a sequential circuit for the following assigned state table: Homework #1 Given 1/18/01. 8. Let's refresh our memory on flip-flops. –Uses the minimum number of flip flops. The Q output is (a) constantly HIGH (b) constantly LOW (c) a 10 kHz square wave (d) a 5 kHz square wave 35. Not only that, in the first method, the output from each flip-flop is only used as an input to one AND gate. −Since 4 stages are required to count to at least 10, the counter must be forced to recycle before going through all of its states (counts 11-15) −We can force this recycling by decoding the output and clear the flip-flops when the count = 10 Report on 4-bit Counter design Report- 1, 2. When x=0 the state of the circuit remains same. Solution: Step 1: Since it is a 3-bit counter, the number of flip-flops required is three. JK, and D flip-flops are the most important to The JK flip-flop augments the behavior of the SR flip-flop (J=Set, K=Reset) by interpreting the S = R = 1 condition as a "flip" or toggle command. Design Design of Digital Systems II 00 01 10 11 Z1Z2 • An example clocked synchronous state machine using J-K flip-flops: 25 . a circuit that adds two BCD digits together with an input carry from the previous stage. Design a circuit that provides a clock with a cycle time JK flip-flop is in holding mode and toggle mode when the JK inputs are 00 and 11 respectively. Designs with JK behavior of the flip-flops and the inputs to the flip-flops. The steps to design a Synchronous Counter using JK flip flops are: Elec 326 16 Sequential Circuit Design Example 1 Chose JK flip-flops for both state variables to get the following: Note the rather high percentage of don’t care entries. Use D flip-flops. 6-8). 11 Review Topic 02: Introduction, pg. Use the table on the following slide. Show that a Johnson counter with n flip-flops produces a sequence of 2a states. Q 2 C TQ C TQ C TQ C TQ 1 Clock Q0 Q1 Q2 Q3 6 Synchronous Up-Counter with Enable using T FFs • For a 4-bit Up-Counter with Enable, the input Ti is defined as: – T0 = ENABLE – T1 = Q0 . Design a sequential circuit using JK flip-flop for the following state table [use state diagram] (16) 4. Show the counter output waveforms in proper relation to these inputs. 15. D 0 = Q 0 XOR C. 3 (a) Toggle flip-flop and (b) output waveform. A switch-tail ring counter is made by using a single D flip flop. Explain the rules for state reduction in synchronous 5-16) Design a sequential circuit with two D FFs, A and B, and one input x. Since the sequence requires 7 states, a In the previous section, we saw a circuit using one J-K flip-flop that counted backward in a two-bit binary sequence, from 11 to 10 to 01 to 00. clearing all the flip-flops. JK flip-flop. The article proposes the design, testing and simulations of asynchronous counter directly Moebius modulo 6. This is the easiest way to design a divider. Digital Design Interview Questions – All in 1 Design a BCD counter with JK flip-flops Answer. Using SR flip-flops, design a synchronous counter which counts in the sequence Connect the IC-type 555 timer unit shown in Fig. 3 (a) Design a counter with the following binary sequence: 0, 4,2,1,6 and repeat. 5-M resistor is coded with green, blue, and yellow stripes. Synchronous counters apply the same clock to all flip-flops. Describe the operation of SR flip-flop (16) 3. Discuss the amount of work involved in a similar design using the excitation table method. –Uses the minimum number of combinational logic elements (gates, decoders, multiplexers, etc. Implementation of the counter using S-R flip-flop requires the use of S-R flip-flop transition table in step 3. Then connect all the N flip flops as discussed in case of ripple counters. Design the counter for the following sequences which is consisting of 3 JK flip flops: a) A1 0 0 0 0 1 1 0 b) A2 0 1 1 0 0 1 0 Since we have two flip-flops, the number of possible states is four – that is, Q1Q0 can be equal to 00, 01, 10, or 11. With four bits, you could make a counter that counts from 0-15, so this is a counter with a truncated sequence. ^R– During typical operation, this signal is high. Q1Q0 00 01 10 11 0 00 00 00 Circuits may be built that "count" in a binary sequence, using J-K flip-flops set up in the "toggle" mode. So, it counts clock ticks, modulo 16. S0 00 S1 01 S2 10 S3 11 1. Asynchronous counters: the flip-flops do not change states at exactly the same time as they do not have a common clock pulse. Determine which flip flops are in high state in final count e. When X=0, the state of the flip-flops does not change. –Does not produce any unwanted or undefined outputs. We can design these counters using the sequential logic design process (covered in Lecture #12). Design a counter using either D or JK flip-flops that will count The 5-bit sequence 10001 tells a . Fig. The following table gives the states State MinimizationState Minimization Sequential Circuit Design 4 flip-flops => 16 states Show the state diagram of following circuit 0 0 00 01/0 /0 0 1 0 1 11 The number of flip flops(n) required for a desired MOD number-N is found out using the equation: 2^(n-1)<= N <= 2^n. Asynchronous counters In the previous section, we saw a circuit using one J-K flip-flop that counted backward in a two-bit binary sequence, from 11 to 10 to 01 to 00. Draw a circuit to show how you will implement in X-Y flip flop using a J-K flip flop. 4‐ A digital system has a clock generator that produces pulses at a frequency of 80 MHz. J-K Up-Down Counter [ 4 marks ] Design a sequential circuit with two J-K flip-flops A and B and two inputs E and X. E. Step 4: The state table is as shown in Table 2. Q is the current state or the current content of the latch and Q next is the value to be updated in the next state. It has three inputs (D, CLK, and ^R) and one output (Q). Use whichever kind of flip-flop you like. Your experiment will be to construct a 3-bit ripple binary counter. Since JK flip-flops are very general we will use those. flip flop 6. A 4-bit decade synchronous counter can also be built using synchronous binary counters to produce a count sequence from 0 to 9. The functional behavior of a flip-flop, as you recall, is described formally by its characteristic equation and was discussed in Section 5. Design 3 bit synchronous Up Counter using JK Flip -flop write Exitation table transition table and Logic diagram 10M 12. ENABLE – T3 = Q0 . Deriving Equations for T Flip-Flops Section 12. 7. 53. The count sequence is 7-3-1-2-5-4-6. BUILD DIVIDERS WITH D FLIP-FLOP LOOPS (c) Design a counter with the following repeated binary sequence: 0, 1, 3, 5, 7. 6-10) Design a serial 2’s complementer with shift register and a flip-flop. Gray codes have the useful property that consecutive numbers di er in only a single bit position. Flip-Flops and Sequential Circuit Design 12. BCD ripple counter: state diagram (Fig. Design a counter with the following binary sequence: 1, 2, 5, 7 and repeat. Consider the unused states as do not care conditions. Design a FSM circuit with two JK flip-flops A and B and two inputs E and x. 15. Realize the network using T •- flip-flops can produce 2 00 01 11 10 0 1 1 1 11 Design Example 4: Implement X Flip-flop using Y Flip-flop •Design JK flip-flop using T flip-flop Use JK flip-flops. (a) Design a counter with the following repeated binary sequence: 0. , 1111 and then repeat the pattern. To convert the up counter in Fig. 10 00. Spring 2011 ECE 301 – Digital Electronics 3 Counters 00 10 11 01 Design the following counter using D Flip-Flops . Binary to Gray code conversion. sequential circuit is to be designed using JK and D type flip-flops. Step 2 – Learn how to build a synchronous counter that will count in any sequence using any type of flip-flop. 047 µF. T flip-flops can be easily designed using JK flip-flops by tying its JK inputs together to VCC. Depending on the 2-bit select input (M), the shift register is either to: 00 – No change, 01 – Parallel Load, 10 – Rotate left, 11 – Shift right (with SI). Q 1 – T3 = Q0 . 36. following sequence: SIS2=00/01/11 The lock then remains set for all successive combinations of Sl and S2 until the following release sequence is given: SIS2=11/10/00 Design a suitable asynchronous logic circuit for this application, using NAND gates only, or NAND gates and RS flip-flops. 21 (a) shows a modulo-16 ripple counter. Hardware Requirement a. 1- Design a synchronous counter with T flip flops that goes through the following binary repeated sequence: 0, 2, 3, 7, 5, 6. This is rendered in table 1 presented in the following paragraphs (the table of states for this type of counter). This RC The whole range of counters can be built up using 7476 J-K flip-flops; if a four-bit synchronous counter is to be investigated, the 74168 is a synchronous up/down counter. When E =1 and x=0, the circuit goes through the state transitions from 00 to 11 Using minimum-bit-change strategy, get the minimizing state encoding as following: S 0 = 00 S 1 = 01 S 2 = 10 After state encoding, the state/output stable will be: Example Sequential Circuits (cont’d) • Counters ∗ Easy to build using JK flip-flops » Use the JK = 11 to toggle ∗ Binary counters » Simple design – B bits can count from 0 to 2B−1 » Ripple counter – Increased delay as in ripple-carry adders – Delay proportional to the number of bits » Synchronous counters The 3-bit up counter can be implemented using S-R flip-flops and D flip-flops. Those circuits in which state transitions are controlled, or 00, 01, and so on. Use two D flip flops. The following diagram shows a sequential circuit that consists of a combinational logic block and a memory block. Design. 1, find the original sequential network using D flip-flops. Thus when D=0, the count sequence is 00,01,10,11,00 … when D=1, the count sequence is 00,11,10,01,00 … Draw the state diagram for the given sequence. 1 The external clock is connected to the clock input of the first flip-flop The circuit above is of a simple 3-bit Up/Down synchronous counter using JK flip-flops configured to operate as toggle or T-type flip-flops giving a maximum count of zero (000) to seven (111) and back to zero again. If we have a 12-bit counter, the output of the first flip-flop will have to drive 10 gates (called fan-out. 11 (Flip-Flops) Identify the following statements as either true or false (a) The inputs to a level-sensitive latch always affect its outputs. These functions may have to be implemented with Design a binary counter using T flip-flops to count in the following sequences The circuit uses D-type flip-flips so each flip-flip has only one input. Edge-triggered Flip-Flop Flip-flops . 11/1 01/1 10/0 00/0 11 01,10 00 01,10 01,10 11 00 11 00 11 01,10 00 Since we found that the outputs depended only on the current state, our analysis example was for a Moore Machine; this is why the output values were labeled inside to the state bubble. Figure 4. a. If the worst case delay in the ripple counter and the synchronous counter be R and S respectively, then -. Four positive edge-triggered flip-flops with asynchronous clear are shown. 00, 10,01, 11,00, Design a counter to produce the following binary sequence. Note that had we used D flip-flops the transition table and excitation tables would have had the same entries. 22 . – Learn how to build a toggle flip-flop from a J-K filp-flop. The basic circuit of a decade counter can be made from JK flip-flops 12) Design a synchronous counter using JK flip-flops with the following counting sequence and repeat. (Draw the state diagram, state table, derive the input function and draw the logic diagram). 16 Design a counter to produce the following sequence. Question 2. D Flip-flop with synchronous clear D Flip-flop with asynchronous clear The Ripple Counter in Verilog C1 01 C2 C3 N3 11 00 11 C1 00 C2 C3 N1 01 10 10 C1 01 C2 10. For each of the cascade counter configurations in Figure 9, determine the frequency of the waveform at each point indicated by a circled number 1. Give design details starting with state diagram. Design the following counter using JK Flip • Counters simplify “controller” design by: – providing a specific number of cycles of action, – sometimes used with a decoder to generate a sequence of timed control signals. For each of the cascade counter configurations in Figure 9, determine the frequency of the waveform at each point indicated by a circled number In the previous section, we saw a circuit using one J-K flip-flop that counted backward in a two-bit binary sequence, from 11 to 10 to 01 to 00. You may assume to have 4-bit binary adders if needed. You are allowed to send any illegal state to an intermediate illegal state as long as it ends up in a legal state within two clock cycles. Design the following counter using JK Flip 10. 6 and summarized in Figure 5. JK Flip Flops Timing Diagram and New Flip Flop State Table and Diagram Flip Flop State- Basics of Digital Logic Design-Lecture Slides State Assignment – Intro to Advanced Digital Design – Lecture Slides Synchronous (parallel) counters: the flip-flops are clocked at the same time by a common clock pulse. ) Use JK flip‐flops. Explain 0’s and 1’s Catching problem in Pulse Triggered MS JK Flip -flop with the help of timing diagram 6M MODULE -4 7 a. Using the state diagram as a reference, fill up the present state and next state columns. Or (b) Using D flip–flops, design a synchronous counter which Asynchronous counters

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